1. Field
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufacturing system.
2. Description of the Related Art
Device isolation regions in semiconductor integrated circuit devices have generally been formed by shallow trench isolation (STI), in place of local oxidation of silicon (LOCOS) isolation.
In the STI, a device isolation trench is etched in a semiconductor substrate, the trench is filled with an insulating layer, and an unnecessary part of the insulating layer is removed by polishing to form a device isolation region. The STI does not produce bird's beaks.
FIGS. 1A to 1G are schematic cross-sectional views of a silicon substrate illustrating steps of forming a device isolation region by STI.
As illustrated in FIG. 1A, the surface of a silicon substrate 101 is thermally oxidized to form a buffer oxide layer 102 of silicon oxide. A silicon nitride layer 103 is formed on the buffer oxide layer 102 by chemical vapor deposition (CVD). The silicon nitride layer 103 functions as a hard mask in substrate etching and as a stopper in chemical mechanical polishing. A photoresist is applied to an organic antireflection layer 104 formed on the silicon nitride layer 103. The resulting photoresist layer is exposed and developed to form a resist pattern 105 having openings in device isolation regions. The antireflection layer 104, the silicon nitride layer 103, and the buffer oxide layer 102 are etched using the resist pattern 105 as an etching mask to form a hard mask. The resist pattern 105 and the antireflection layer 104 are then removed.
As illustrated in FIG. 1B, the silicon substrate 101 is etched using the hard mask as an etching mask to form trenches T.
As illustrated in FIG. 1C, silicon surfaces of the trenches T are thermally oxidized to form silicon oxide liners 106.
As illustrated in FIG. 1D, the trenches T are filled with a silicon oxide layer 107 by high-density plasma (HDP) CVD.
As illustrated in FIG. 1E, an unnecessary part of the silicon oxide layer 107 is removed by chemical mechanical polishing (CMP) using the silicon nitride layer 103 as a stopper to expose the silicon nitride layer 103. An active region is covered with the buffer oxide layer 102 and the silicon nitride layer 103.
As illustrated in FIG. 1F, the silicon nitride layer 103 is removed by wet etching using boiling phosphoric acid. The buffer oxide layer 102 and the silicon oxide layer 107 are etched negligibly.
As illustrated in FIG. 1G, the buffer oxide layer 102 is removed using a hydrofluoric acid solution. The silicon oxide layer 107 in the device isolation regions is also etched. The height of the silicon oxide layer 107 in the device isolation regions is controlled by over-etching of silicon oxide. Subsequent steps involve thermal oxidation of the surface of the active region, ion implantation to form wells, and removal of an oxide layer. The surface of the active region is then oxidized to form a gate insulating layer. The formation of gate insulating layers having different thicknesses involves selective removal of a gate insulating layer and formation of a new gate insulating layer. The silicon oxide layer in the active region is etched together with the silicon oxide layer in the device isolation region.
When the height of the STI silicon oxide layer (STI oxide layer) 107 is controlled by over-etching of silicon oxide in the step of removing the buffer oxide layer 102 with a hydrofluoric acid solution, isotropic etching of the STI oxide layer 107 may cause a divot in an area surrounding the STI oxide layer 107. The formation of a deep divot may reduce the processing accuracy.
Japanese Laid-open Patent Publication No. 2002-151465 proposes that the thickness of an STI oxide layer should be controlled after CMP is performed in an STI process. Since the top surface is etched while a hard mask remains, a flat surface can be formed.
A hard mask layer composed of a polysilicon film and a silicon nitride film is formed on a buffer oxide layer. Steps corresponding to those illustrated in FIGS. 1A to 1E are preformed to form a flat surface by CMP. On the basis of the thickness of an exposed STI oxide layer, the silicon oxide layer is etched to have a desired thickness. The hard mask layer is then etched. The STI oxide layer can be etched with high precision after the thickness thereof is measured.
Japanese Laid-open Patent Publication No. 2004-71862 discloses a process for manufacturing a semiconductor device including the steps of forming a stopper layer of silicon nitride on a buffer oxide layer, performing steps corresponding to those illustrated in FIGS. 1A to 1E to expose the stopper layer by CMP, measuring the thickness of the stopper layer, and determining the wet-etch depth in the STI oxide layer on the basis of the average thickness of the stopper layer. The thickness of the STI oxide layer formed on the stopper layer and the thickness of the stopper layer removed by CMP depend on the area of an active region. Thus, measurement of the thickness of the stopper layer after CMP and before etching of an embedded oxide layer can reduce variations in STI height between individual wafers or lots of wafers. The layer whose thickness is to be measured is the embedded oxide layer in Japanese Laid-open Patent Publication No. 2002-151465 or the stopper layer in Japanese Laid-open Patent Publication No. 2004-71862.
Japanese Laid-open Patent Publication No. 2007-109966 discloses a process for manufacturing a semiconductor device including the steps of forming a stopper layer of silicon nitride on a buffer oxide layer, performing steps corresponding to those illustrated in FIGS. 1A to 1E to expose the stopper layer by CMP, removing the stopper layer by 50% or less of the initial thickness thereof, and wet-etching the STI oxide layer by 10% to 50% of the initial thickness of the silicon nitride stopper layer.
In another field of the art, the formation of multilayer interconnection on an interlayer insulating layer disposed on a silicon wafer may cause the silicon wafer to be warped outward owing to the stress caused by the interlayer insulating layer. The warping of the wafer increases with increasing wafer size.
Japanese Laid-open Patent Publication No. 2006-4982 discloses a process for manufacturing a semiconductor substrate including the steps of forming silicon oxide layers on the front and back sides of a silicon wafer by thermal oxidation, specifically, placing a plurality of silicon wafers in a vertical furnace, forming silicon nitride layers and silicon oxide layers on the front and back sides of the silicon wafer by batch-wise thermal CVD, and removing the silicon oxide layer formed on the front side of the silicon wafer by wet-etching using hydrofluoric acid. The silicon nitride layer formed on the front side of the silicon wafer functions as an etching mask and a CMP stopper. The silicon nitride layer formed on the back side of the silicon wafer prevents the silicon wafer from being warped. The silicon oxide layer formed on the silicon nitride layer on the back side of the silicon wafer functions as a layer that protects the silicon nitride layer on the back side of the silicon wafer while the silicon nitride layer on the front side of the silicon wafer is removed with hot phosphoric acid.
When the thickness of an STI oxide layer is controlled before the stopper layer is removed, the thickness of the STI oxide layer can be controlled by etching from above. However, even in this case, a gate electrode may not be patterned precisely.